Availability of high-resistivity silicon substrates has provided a major new opportunity for developing and marketing RF components, especially integrated passive devices (IPDs). Due to compatibility with established integrated circuit (IC) manufacturing technology, availability, and cost, HRS has turned out to be an nearly ideal substrate for RF-IPDs.
However, surface effects continue to pose issues, partially masking the potentially low RF loss levels in obtainable with advanced HRS substrates. Namely, charges trapped at the silicon-dielectric interface or within the dielectric layer itself can create accumulation or inversion layers, which enable parasitic surface conduction channels to be generated. These parasitic channels generate stray currents in an RF field. These stray currents, in turn, increase transmission line attenuation, reduce obtainable Q-factors in inductors, and reduce the selectivity of filters manufactured on this substrates.
Methods have been devised to overcome the performance limitations posed by these surface effects. Most commonly used methods are a relatively heavy implantation with neutral species such as argon, silicon, neutrons, or protons (M. Spirito, F. Maria de Paola, L. Nanver, E. Valletta, B. Rong, B. Rejaei, L. C. N. de Vreede, J. J. N. Burghartz, “Surface-Passivated High-Resistivity Silicon as True Microwave Substrate” IEEE Transaction on Microwave Theory and Techniques, Vol. 53, No. 7, July 2005; Chan, K. T., Chin, A., Chen, Y. B., Lin, Y. -D, et al, “Integrated antennas on Si, proton-implanted Si and Si-on-quartz” IEDM '01 Technical Digest, IEEE International, 2001) and a deposition of amorphous polysilicon layers (B. Rong, J. N. Burghartz, L. K. Nanver, B. Rejaei, and M. van der Zwan, “Surface-Passivated High-Resistivity Silicon Substrates for RFICs” IEEE Electron device letters, Vol. 25, No. 4, April 2004) on top of the HRS substrates. An amorphous/polysilicon deposition has also been applied to handle wafers used in SOI manufacturing (D. Lederer and J. -P. Raskin, “RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate,” IEEE Transaction on Electron Devices, July 2008). Suppression effect in all of these methods is based on enhanced trapping of charge carriers within the implanted or polysilicon layer on a top of the HRS substrate.
However, all these methods induce additional cost effects, and they pose limitations in HRS-based device processes. These issues have limited the viability of these methods.